1. Field of the Invention
The present invention relates to a scan test circuit that, when incorporated into an integrated circuit, provides improved fault coverage while reducing the necessary amount of test circuitry. More particularly, the invention relates to the resetting of flip-flops in a scan test circuit.
2. Description of the Related Art
Scan test circuits include scan flip-flops equipped with multiplexers that can select either normal data input or scan data input. A plurality of such scan flip-flops may be chained to operate as a shift register. Arbitrary test data can be loaded into a chain of scan flip-flops in a scan shift sequence, and output to a combinatorial circuit. The scan shift sequence is followed by a capture sequence in which further scan flip-flops (or the same flip-flops) latch data output from the combinatorial circuit, thereby determining how the combinatorial circuit processed the test data.
A challenge faced in scan testing is designing test data to provide high fault coverage, that is, to detect a high percentage of anticipated faults in the combinatorial circuit. The challenge is made more difficult by the presence of flip-flops, not synchronized with the scan flip-flops, that may conceal the operation of combinatorial circuit elements during a scan test. Japanese Unexamined Patent Application Publication No. 2001-296331 discloses a scan test circuit having a test enable input signal that enables such flip-flops to be bypassed. Japanese Unexamined Patent Application Publication No. 2002-267719 discloses a scan test circuit having special scan control flip-flops or exclusive-OR gates that increase the number of points at which signals output from the combinatorial circuits can be observed.
The scan flip-flops may also have asynchronous reset terminals, which pose a further challenge during the scan test process. Some scan test circuits generate an internal reset signal, which must be held in the inactive state during the scan shift sequence. Some of these scan test circuits also receive an external reset signal which is selected and held inactive during the scan shift sequence, and may be controlled arbitrarily for test purposes during the scan capture sequence.
A general problem with many known scan test circuits is that an integrated circuit incorporating them requires extra pins for input of signals such as the external reset signal, the test enable signal, or other test mode signals. By increasing the necessary number of test patterns, these extra pins increase the cost of scan testing. The extra pins also increase the size and fabrication cost of the integrated circuit, and the added circuitry they entail leads to lowered fault coverage and lower reliability. The same is true of scan test circuits with special scan control flip-flops or extra exclusive-OR gates.